Ab­stract

Ad­vances in SOI tech­nol­ogy such as STMi­cro’s 28nm UTBB-FD­SOI en­abled a re­nais­sance of body bi­as­ing. Body bi­as­ing is a fast and ef­fi­cient tech­nique to change power and per­for­mance char­ac­ter­is­tics. As the elec­tri­cal task to change the sub­strate po­ten­tial is small com­pared to Dy­namic Volt­age Scal­ing, much finer is­land sizes are con­ceiv­able. This how­ever cre­ates new chal­lenges in re­gard to de­sign par­ti­tion­ing into body bias is­lands and body bias com­bi­na­tions across such de­signs. These com­bi­na­tions should be cho­sen so that en­ergy ef­fi­ciency im­proves while main­tain­ing tim­ing con­straints. We in­tro­duce a com­bi­na­tion based analy­sis tool to find op­ti­mized body bias is­land par­ti­tions and body bi­as­ing lev­els. For such par­ti­tions, op­ti­mized body bias as­sign­ments for sta­tic, pro­gram­ma­ble and dy­namic body bi­as­ing can be com­puted. The over­heads in­curred by dy­nam­i­cally switch­ing body bi­ases are es­ti­mated to yield ac­tual im­prove­ments and to give an upper bound for the power con­sump­tion of re­quired ad­di­tional cir­cuitry. Based on these par­ti­tion­ings and the switch­ing over­heads, op­ti­mized ap­pli­ca­tion spe­cific switch­ing strate­gies are com­puted. The ef­fec­tive­ness of this method is demon­strated in a fre­quency scal­ing sce­nario using for­ward body bi­as­ing on a Dy­namic Re­con­fig­urable Proces­sor (DRP) de­sign. We show that leak­age can be greatly re­duced using the pro­posed meth­ods and that dy­namic body bi­as­ing can be ben­e­fi­cial even at small time pe­ri­ods.